1. Field of the Invention
The invention relates to a method for producing an epitaxially coated semiconductor wafer.
2. Background Art
One extremely important parameter of a semiconductor wafer, on which ever-increasing demands are being placed (cf. ITRS “International Technology Roadmap for Semiconductors”), is its nanotopography. The nanotopography is conventionally expressed as a height variation PV (=“peak-to-valley”), based on square measurement windows with an area of 2 mm×2 mm.
In order to study nanotopography, the Nanomapper® instrument from KLA Tencor is suitable, for example this interferometer is suitable for measuring the topography in the range of from −20 nm to +20 nm on the frontside of the semiconductor wafer. During the measurement, the semiconductor wafer is placed on a soft, flat wafer holder (chuck). The resulting peak-to-valley (PV) values are filtered (Gaussian highpass filter) and analyzed on circles with a diameter of 2 mm (also on circles with a diameter of 10 mm) with respect to peak-to-valley deviations. In the THA (“threshold height analysis”) analysis (for details see SEMI standard M43), the 3 sigma PV value is ultimately calculated from the distribution of all the PV values as a so called THA value. Often, the THA value is also referred to as THA 2 in order to make it clear that small analysis windows with a diameter of 2 mm have been used.
For electronics, microelectronics and microelectromechanics, semiconductor wafers with extreme requirements for global and local planarity, one side referenced local planarity (nanotopography), roughness and purity are required as starting materials (substrates). Semiconductor wafers are wafers of semiconductor materials, in particular compound semiconductors such as gallium arsenide and mainly elementary semiconductors such as silicon and sometimes germanium. According to the prior art, semiconductor wafers are produced in a multiplicity of successive steps, which can generally be divided into the following groups:    a) producing a monocrystalline semiconductor ingot (crystal growth);    b) cutting the ingot into individual wafers;    c) mechanical processing;    d) chemical processing;    e) chemical mechanical processing;    f) optionally, production of layer structures.
The crystal growth is carried out by pulling and rotating a preoriented monocrystalline seed from a silicon melt, the so-called CZ (“Czochralski”) method, or by recrystallization of a vapor-deposited polycrystalline crystal along a melt zone generated by means of an induction coil, which is slowly moved axially through the crystal, i.e. by the so-called FZ (“floating zone”) method.
It is known in the prior art of CZ crystal pulling that a growth interface shape characteristic of the respective process parameters is formed in a complex interaction of melt convection or diffusion, dopant segregation at the growth interface and thermal conduction and radiation of the melt and the ingot. The complex material transport phenomena in the melt and during the material deposition at the phase interface lead to a spatially varying concentration of the dopant deposited in the growing semiconductor single crystal.
Owing to the rotational symmetry of the pulling process, pulling device and growing semiconductor ingot, the dopant concentration variations are substantially radially symmetrical. That is to say, concentric rings of varying dopant concentration are formed along the symmetry axis of the semiconductor single crystal. These dopant concentration variations are also referred to as “striations,” and can be revealed by measuring the local surface conductivity or structurally as nonplanarity after treatment with a defect etch.
Sawing the semiconductor rod to separate it into individual semiconductor wafers leads to near surface layers of the resulting semiconductor wafers whose monocrystallinity is damaged. These damaged layers are subsequently removed by chemical and chemical mechanical processing.
The material removal rate in chemical or chemical mechanical processing of the surface of a semiconductor wafer depends on the local chemical or electronic properties of the semiconductor surface. Annular nonplanarities are formed in the surface of the silicon wafer, according to the dopant concentration variations. This concentric height modulation of the surface after chemical or chemical mechanical processing is also referred to as “striation.”
Semiconductor wafers suitable as a substrate for particularly demanding applications in electronics, microelectronics or microelectromechanics must have a particularly high degree of planarity and homogeneity of their surface. This is because the planarity of the substrate wafer crucially limits the achievable planarities of the individual circuit planes of typical multilayer components, which are subsequently structured on the surface photolithographically. If the starting planarity is insufficient, then breakthroughs of the applied insulation layers will occur later during the various processes of planarizing the individual wiring planes, leading to short circuits and therefore failure of the components thus produced.
For this reason, semiconductor wafers which have small and long wavelength dopant concentration variations as far as possible, are preferred by the prior art. This more desirable dopant concentration variation can be achieved by pulling at particularly slow pull rates, in order to maintain a necessary particularly flat growth interface. Such processes, however, are laborious and uneconomical.
Semiconductor wafers are often provided with an epitaxial layer, i.e. with a layer deposited in monocrystalline form with the same crystal orientation, onto which semiconductor structures are subsequently applied. Such epitaxially coated semiconductor wafers have certain advantages over semiconductor wafers made of homogeneous material, for example the prevention of charge reversal in bipolar CMOS circuits due to short circuit of the component (“latch up” problem), low defect densities (for example a reduced number of COPs (“crystal originated particles”)) and the absence of a significant oxygen content, so that the risk of short circuits due to oxygen precipitates can be excluded in regions relevant for the components. However, ring structures on the surface are also observed in epitaxially coated semiconductor wafers. These also lead to a comparatively poor nanotopography (THA 2 value, cf. above).